1. Technical Field
The present invention relates to a semiconductor device, and particularly relates to a semiconductor device having an electrode pad such as a flip-chip pad and the like and a capacitor element.
2. Related Art
Increased scales and increased integrations are progressed in semiconductor devices of recent years, and number of signal pads and number of power supply pads are increased. Further, under a circumstance of increased operating rate of devices, improvements in electrical characteristic of devices such as impedance matching and the like between a semiconductor device and mounting substrate or package substrate are more critical. A flip-chip mounting becomes a mainstream of measures for solving such problems. The flip-chip mounting is a packaging scheme, which can achieve arranging pads across the entire surface of the semiconductor device, or more specifically, arranging multiple pads. Further, the flip-chip mounting can provides an improved electrical characteristics of devices over the packaged substrate or package substrate.
FIG. 11 is a cross-sectional view, illustrating a configuration of a conventional flip-chip pad (also referred to as FCPAD). A flip-chip pad shown in FIG. 11 is formed according to the following procedure.
First of all, an interlayer film 203 and an uppermost layer interconnect 205 are formed on a semiconductor substrate 201 having semiconductor elements and interconnects formed therein, and a cover film 207 for protecting the semiconductor devices is formed thereon. Next, only a portion on the uppermost layer interconnect 205 of the cover film 207 coupling to the flip-chip pad 211 is selectively removed to provide a pad via 217 extending through the cover film 207.
Subsequently, the flip-chip pad 211 is selectively formed in a region for forming the pad via 217 and the vicinity thereof. A solder ball 213 is, in turn, selectively formed on the flip-chip pad 211. Finally, though it is not shown in FIG. 11, the terminals in the side of the packaged substrate or the package substrate are coupled to the solder ball 213 to complete the flip-chip package.
Meanwhile, increased scales, increased integrations and increased operating rates are progressed in semiconductor devices, and a defectives in circuit operations due to a noise in power/signal such as cross talk or the like become more serious issues than before. Countermeasures for the issues is a method for inhibiting a noise by forming a capacitor element on a semiconductor device, and adding a capacitance to other required portion in a power supply or the like. In addition, processes for forming a capacitor element includes a process utilizing a semiconductor substrate and a process utilizing an interconnect process, and in recent years, a metal-insulator-metal (MIM) capacitance is often manufactured via the process utilizing the interconnect process, which provides relatively higher degree of design flexibility and higher density of capacitances.
Typical conventional technologies concerning the capacitor element includes technologies described in Japanese Patent Laid-Open No. 10-313,095 (1998), Japanese Patent Laid-Open No. 2002-353,328, Japanese Patent Laid-Open No. 2004-266,005, Japanese Patent Laid-Open No. 2001-313,372, Japanese Patent Laid-Open No. 2002-57,291, and Japanese Patent Laid-Open No. 8-186235 (1996).
A technology for forming a capacitance under a pad is described in Japanese Patent Laid-Open No. 10-313,095. FIGS. 12A and 12B are diagrams, illustrating a configuration of a device disclosed in Japanese Patent Laid-Open No. 10-313,095.
In a structure of FIGS. 12A and 12B, a silicon oxide film 3 serving as a capacitive film is formed on a well 14 formed in a single crystalline silicon substrate 1, and a first polycrystalline silicon interconnect 4, which would be employed as a gate electrode in the ordinary case, is formed thereon to form a capacitor element. Further, a contact hole 7, a first (aluminum) metallic interconnect 8 and a second (aluminum) metallic interconnect 9 are formed on the first polycrystalline silicon interconnect 4, and an aluminum bonding 16 is provided thereon to form a capacitor element under a pad.
However, in the configuration shown in FIG. 12, no transistor or no interconnect can be formed on portions having capacitances formed thereon. Thus, recently, MIM capacitances formed via the interconnect process are often employed.
FIG. 13 is a diagram, illustrating a configuration of a MIM capacitance described in Japanese Patent Laid-Open No. 2002-353,328. A configuration shown in FIG. 13 involves that, in the process for forming an underlying interconnect layer 2A, an underlying metallic layer 2B formed in a multiple-layered film is also simultaneously patterned, and a dielectric material layer 3A is formed thereon. Further, an overlying metallic layer 4 is formed thereon, and is selectively patterned to form a capacitor element between the underlying metallic layer 2B and the overlying interconnect layer 4. Thereafter, via holes 7a to 7d and 11a which provide couplings between respective interconnects and between electrodes, interconnect lines 7A to 7D, and 11, and upper interconnect layer 9A to 9 C are formed.
FIG. 14 is a diagram, illustrating a configuration of a MIM capacitance described in Japanese Patent Laid-Open No. 2004-266,005. In the configuration shown in FIG. 14, a first aluminum interconnect 3 and an anti-reflection film 4 are formed, and then a second insulating interlayer 5 is formed. Next, an ordinary contact plug 82 is opened to expose a surface of the first aluminum interconnect 3, and an upper electrode 81 of a capacitance is opened to expose a surface of the anti-reflection film 4.
Then, respective openings are filled with barrier metals 7 and metallic electrodes, and further a second aluminum interconnect 10 is formed thereon. This provides a coupling between the first aluminum interconnect 3 and the second aluminum interconnect 10 via the contact plug 82, and a capacitor element having a capacitive film composed of a titanium nitride (TiN) layer 41 and a silicon oxynitride (SiON) layer 42 of the anti-reflection film 4 is formed between the first aluminum interconnect 3 and the upper electrode 81.
Further, a technology for forming a MIM capacitance between metallic layers by employing a copper wiring process according to a damascene process is described in Japanese Patent Laid-Open No. 2001-313,372. It may be considered that such technology is an advanced version of the technology described in Japanese Patent Laid-Open No. 2004-266,005. While the technology described in Japanese Patent Laid-Open No. 2004-266,005 involves separate processes for forming the contact plug coupling the upper and the lower plates and for forming the overlying plate via a single damascene process, the technology described in Japanese Patent Laid-Open No. 2001-313,372 involves a single process for simultaneously forming the contact plugs and the overlying plate via a dual damascene process. Further, while the technology described in Japanese Patent Laid-Open No. 2004-266,005 includes the upper plate coupled to an interconnect of the overlying layer, the technology described in Japanese Patent Laid-Open No. 2001-313,372 includes the upper plate coupled to the underlying interconnect.
A technology for forming a rerouting above a coupling pad, and then forming a capacitor element therebetween is described in Japanese Patent Laid-Open No. 2002-57,291.
A technology for forming a memory cell transistor and a memory capacitor on different substrates, and then bonding these substrates to form a dynamic random access memory (DRAM), is described in Japanese Patent Laid-Open No. 8-186235. In a circuit structure of such DRAM, one of terminals of a memory capacitor is coupled to a memory cell transistor, and the other is coupled to a ground.